I.Capacitance transient method

The principle of the study of capacitance transients consists of the study of the kinetics of the return to equilibrium of the capacitance of a MOS structure after the application of a voltage step. The return to equilibrium is controlled by the kinetics of the capture or emission of electrons and holes by localised traps in the depletion region and in the oxide-semiconductor interface. By employing certain simplifying hypotheses, this method, when'used in different forms, enabled the measurement of the characteristic values of these traps: concentration, energy level, capture cross sections and emission time. In general, this method gave better results than the traditional methods (high-frequency C-V, quasi-static C-V) in that it enables the density of traps to be measured within the range 10 8 - 10¹⁰/cm². However, there are opposing opinions with regard to the experimental values put forward by different authors (1)(2)(3), which on the one hand reflects the complexity of transient phenomena within MOS structures, and on the other hand shows that the models used are far from being satisfactory.

Let us consider a general MOS structure (Fig. I-a) and apply a set voltage step. In the first instance, only the majority carriers react to the excitation, thus contributing to the formation of a wide depletion region (Fig. I-b). Given that the system is out of equilibrium and because of the configuration of the electric potential in the structure, all minority charges generated in this region are unstable and are repelled towards the interface, where they contribute to the formation of the inversion layer. The majority charges will be drawn towards the limit of the depletion region, where they reduce the width of this region by neutralising the ionised impurities. Interface conditions also play a role in this transient stage by the processes of emission and generation-recombination (Figs. I-b,c). It is clear that the return to equilibrium is established after the formation of the inversion layer, the kinetics of which is controlled by the lifetime of the minority carriers. In experimental terms, one proceeds by recording the development of the depletion region₁ the thickness of which is closely linked to the kinetics of formation of the inversion region. The lifetime of the minority carriers is derived from the development of the inversion layer.

The study itself is limited to measuring the total capacity of the system and useful physical parameters can be obtained by the mathematical calculation detailed in the following section.

I.a.Mathematical formulation (Zerbst) (1)

By applying Gauss' law to the MOS structure at a given moment during the transient period, Zerbst, ignoring the potential drop across the inverse region, links the development of the density of the charge of the inversion region with the relaxation of the depletion region.

Dni/dt = -(Cox/Es*W+1)*Nb*dW/dt (1)

- N₁ density of instantaneous charge of inversion layer Lcm-² I

- Cox = oxide capacitance LF/cm²]

- w = instaneous thickness of depletion region L cm3

- NB = dopant density

- Es = permittivity of silicon C/V/cm

- W is obtained experimentally from the value of CHF.

- CHF: total capacitance of the MOS system at high frequency (1MHz).

W(t)=Es(1/Chf-1/Cox) (2)

from which with Eq (1):

Dni/dt=-NbEs/eCox..d(Cox/Chf)E2/dt (3)

and

Ni=CoxU/q - NbEs/2Cox((Cox/Chf)E2-1) (4) U = voltage step q = electron charge. XE2=x*x

Moreover, Zerbst suggest that the variation of N₁ is controlled by two independent components, i.e. the generation in the depletion region and that of the surface: Dni/dt= qSni + qni/C*(W-W0) (5) ni = intrinsic concentration of electrons and holes. S = generation velocity (sec~¹ ) In terms of capacitance, this relationship becomes: -d/dt(Cox/Chi)E2 = eCox/NbEs*qniS + eCoxni/tauNb(1/Chf - 1/Cinf) (6) Cinf = capacitance of the MOS structure in equilibrium. This formula thus enables the determination of tau and S, respectively, the lifetime of the minority carriers and the generation rate of the surface. It obviously involves a simplified relationship; other sources of current can contribute to N₁ (Fig. 2), in paticular: - current from the generation by light - diffusion current coming from the substrate - generation in the depletion region resulting from implantation damage, for example close to the surface (dislocations -stacking - faults) - lateral generation in the peripheral region.

The contribution of the first two factors can be controlled by working in a dark space and at low temperature (ambient temperature in the case of a silicon substrate). The fourth factor is influenced by the geometry of the MOS structure and can also be controlled by using special structures (2).

Other variations on the Zerbst method have been proposed, either to simplify the working of the experimental measurements (3), or simply to take one of the above-mentioned factors into account. However, there are still problems with regard to the application of the capacitance transient method, i.e. the non-reproducibility of the measurements and the absence of the linear section in the curve in certain structures.

-d/dt(Cox/Chf)E2 = f(Cinf / Chf - 1) (7)

Having arrived at this stage, it is useful to try a new approach; this approach does not focus on the development of the inverse layer as a function of the thickness of the depletion region. As stated above, the linear section (Zerbst relation) is often absent and another mechanism or interfacial generation prevails. The approach followed here is to study the development of the displacement current as a function of the corresponding displacement charge tj~~NI) = f(N₁), a procedure applied in the study of the characteristics of the traps in the oxide (4). The advantage of this approach is to be found in the fact that theoretically it enables the separation of the volume factors and the surface factors. In fact, each process which plays a role in the formation of the inversion layer is distinguished by the specific behaviour of d/dt(Ni) = f(Ni). Let us consider each process individually in order to characterise its own profile in terms of

a)Volume effect:

Eq(4) gives Ni prportional to (Cox/Chf)E2

Eq(6) gives dNi/dt prportional to (Cox/Chf)

Which means that dNi/dt proportional to sqr(Ni) (8)

b) Surface effect:

I) emission

dni/dt = Ni/tau (9)

by relaxation of occupation of the trap levels of the interface.

2) interfacial generation:

Dni/dt = ni*S = constant (10)

The result is that the analysis of the log d/dt(Ni) vs log N₁ enables us to specify the contribution of each component to the formation of the inversion layer, in particular when the Zerbst method is not applicable.

II. Experimental section

In order to test this procedure, the log (d~~~>s f(log N₁) curves of numerous wafers of various origins were recorded. The selected capacitances had been characterised beforehand by the traditional methods (high-frequency c-V, quasi-static c-V) in order to determine the thickness of the oxide layer, the dopant concentration, the Fermi level, the flat band voltage, and in particular the concentration of the fixed oxide charges and that of the interface states.

The measurement equipment used is presented in figure 3. It consists basically of:

- A thermal chuck equipped with a vacuum pump to guarantee the mechanical stability of the device to be analysed. - A pulse generator with programmable voltage (HP8116A) equipped with an internal synchronisation function. It can produce voltage pulses as short as approximatley 10 ~s. - A capacitance meter (HP4280A), designed to measure capacitance values up to I MHz as a function of time, equipped with an internal inipulse generator. All the equipment is controlled by a microcomputer which enables us, among other things, to analyse and record data automatically.

III. Results

111-1 Measurement reproducibility

In the first place we considered the reproducibility of the measurements to be very important in order to define the experimental requirements and to avoid interference phenomena. This study was carried out either by comparing the curves of log ( d/dt(Ni) vs log N₁ of various capacitances of the same wafer, or by carrying out repe~itive measurements on a carefully selected capacitance. Figures (4-5-6) show that on the one hand the measurements are only reproducible if low voltage steps ( IuI <~ V) are used. Moreover, the curves recorded for the different capacitances of the same wafer only show a slight

dispersion, which is probably inherent in the process. One point noted is that the defective capacitances are easily detected, since they have a large constant current. For voltage steps above 3V, it was found that the inversion current increases with the number of measurements carried out on a given capacitance. This behaviuor has been observed in wafers of different origins. This enabled us to put forward the view that at the time of the C-t measurements, the MOS structure undergoes an electrical stress sufficient to modify the amount of interface states. In order to verify this hypothesis, quasi-static C-V measurements were made in between the C-t measurements, thus enabling us to follow the development of the interface states qualitatively. The 1/C² vs V curves in figure (7) measured before and after a C-t measurement show that effectively the MOS structures are not insensitive to the effects of electrical loads voltage steps of approximately 5V. A hysteresis normally associated with interface conditions is observed.

It is noted that the effects are not cumulative, probably because of a compensation process. The effect of electrical stress on C-t curve will be discussed in detail later.

111.2. Effect of the geometry of the MOS structure

In this section, we tested circular and rectangular structures with different areas (Fig. 8) in order to study the interference effects of corners and lateral generation. The curves (Fig. 8) show that these factors have a certain contribution to the current. It is however quite low in view of the main volume and interfacial contributions. The increased noise of the curves should also be noted; this is found in the structures with a large surface area and is possibly caused by fluctuations of the surface potential. Table I summarises the results obtained, in particular the physical parameters obtained from the curves.

111.3. Effect of electrical parameteres

a) Effect of U = V~ : voltage step prior to the measurement.

The effect of V~ was studied on three MOS structures with different characteristics: - non-implanted MOS structure as a reference - MOS structure implanted by 0+ characterised by a high concentration of interface states - MOS structure with a guard ring to prevent lateral generation.

The results obtained are presented in the figures (9-10-11) and show that, independently of V~, the current increases with the number of measurements in the case of the first structure; the independence is obvious in the other structures. We can conclude from the results that the process of emission from the surface is poor, probably due to the low concentration of interface states below the Fermi level.

111.4.Effect of V_1~: measurement voltage

The effect of Vm was tested on a MOS structure implanted in 0+. The results in figure (12) show a clear extension of the linear section for the increasing voltages Vm. It is also found that the slope of the curve is independent of Vm. Among other things, the contribution of the "lump" increases considerably with voltage Vm With regard to the extension of the linear section, it reflects the importance of the volume contribution for high voltages. The shift of the "lump" with voltage V should also be noted; it is found towards increasingly lower values of N₁ as voltage increases. This fact is clearly shown in the MNOS structures (Fig. 13).

111.5. Effect of the concentration of the interface conditions

The separation of the volume contributions and the surface generation is a vital problem in the capacitance transient method. To solve this problem, it is advisable to test the MOS structures with different concentrations of interface states. These were obtained either by implantation of oxygen 0+ and of argon A+ in the oxide, or by submitting the structure to electrical stress by injecting charges of approximately several fractions of the charge needed for breakdown.

III.5.a. Effect of the implantation

The MOS.structures studied were manufactured wafers of Si (100) of type p (17-23~cm). The main stages of the technological process are: thermal oxidation and local etching to obtain thick layers of oxide (6000 A⁰) and thin layers of gate oxide (300 A⁰). 0+ or Ar+ implantation at 10 KeV. - 0.5 ~m gate of silicon polycrystalline doped with P+ by implantation (5.10-~ at 50 KeV). - I ~m Al-Si 1% for the ohmic contact of the substrate. Table (II) summarises the main electrical properties of the structures tested and the curves (14-15) show the corresponding profiles log(L;^4~7)vs f (log N₁). According to these curves, it is found that the curves obtained are strongly influenced by the dose of oxygen implantation. The effect of argon is slight in the range of the dose used and affects essentially the slope. The results of the c-V measurements (Fig. 16) correspond with the previous findings where it is shown in fact that the concentration of the interface conditions is proportional to the implantation dose of oxygen. This is probably due to the strong reactivity of this element at the interface, which is also found when comparing the oxide thickness of the different structures studied, proportional to the implantation dose of

III.5.b. Effect of electrical stress on MOS structures

The procedure used to study the effect of electrical stress consists of injecting a constant current for a set period of time in accordance with the required injection charge. The curves in figure (17) show the log ('/~/;/6) vs log N₁ curves of the MOS struture or p-type Si before and after injection of the charge. These results show that while the effect of the injection after positive current is clear, shown by a monotonic increase of d'~/-it as a function of the charge injected, that of the negative current remains small, even for injections up to 5.7.10Exp(-5) C/cm² (fig.18). In general, the value of decreases after a negative current. Figure (19) also shows the effect of stresses on the Zerbst plot.

IV.Effect of temperature

In order to draw conclusions on the mechanism of thermal generation in the capacitance transient method, we studied the current variation as a function of temperture.

This method enables us in particular to verify the hypothesis used in Zerbst's calculation where the thermal generation in the neutral region is assumed to be negligible. We should not forget that this hypothesis has been disputed by certain authors (5); on the basis of a simulation study, they concluded that the capacitance transient phenomenon is controlled by the diffusion of the neutral region of the MOS structure and that the values obtained from Zerbst's calculation ( ~,S) do not reflect their physical significance in a single case. We obtained the curve log(dNi/dt)=f(1/tau) (Fig. 21) from the profiles of figure (20). Figure 21 shows an activation energy equal to 0.55 eV close to that of ni (deltaHni - 0,6 eV, ni being the intrinsic concentration of the electrons and the holes) in the temperature range 20⁸C-70⁰C, and consequently is consistent with Zerbst~s hypothesis. If thermal generation in the neutral region controls the generation, this would results in a relationship of the type dNi/dt = constant x Ni². Hence an activation energy of 1.2-1.3 eV would be observed.

V.Application of the capacitance transient method to the MONOS structures

Two types of MNOS structure were analysed in this study: - structure bilayer -SiO2 : 620 A -Si ₃N4: 750 A - structure bilayer SiO₂ : 800 A - Si₃N4: 400 A numbered 1 to 17.

A preliminary study of these structures, using the traditional methods (high-frequency C-V, quasi-static c-V) enabled us to demonstrate the effect of the nitride on the electrical properties of MNOS structures. Table (III) summarises the main results obtained; it should be noted that the measurements were taken on the C module. The A modules of wafers 11 and 20 were also studied. The results obtained show a very low concentration of the interface states which can be seen in all the wafers analysed. This proves once more the beneficial effect of nitride with regard to its resistance to the diffusion of impurities₁ which gives better results than that of 5i0₂ (6). The table shows, among other things, that the effect of the thickness of the nitride only affects the VfB and Nf values, respectively, the flat band voltage, and concentration of fixed oxide charges, where the low values of Nf were found in the MNQS structures with a nitride thickness of 750 A.

The curves of log(~~/t)vs log (N₁) of certain wafers are shown in.figures (22, 23); they do not correspond in a single case to those predicted by Zerbst. The dependence between current and charge of the inversion layer is slight and this is also the case for the relationship between inversion current and the development of the thickness of the depletion region. With the exception of certain anomalies which are frequent in the structures of the A module, and probably characteristic of the structure of the oxide, the profiles obtained are of the type dA'~4i~ = constant. It should be noted that this type of profile has also been found in MOS structures.

VI.2. Effect of covering the gate and the oxide in a MNOS structure

The MNOS A and C structures tested are shown in figure (23). Module A can be distinguished from C by a gate which covers the thin oxide entirely. Because of the geometry of these modules, a greater concentration of interface states is obtained in the A-type structure, for the annealing of these states may be less efficient in a structure of this type. The traditional CV measurements (high-frequency and quasi-static) did not enable us to show this difference, probably because of the very low concentrations of interface states found in these structures; approximately i0⁹ cm~² is the limit of the resolution capacity of these methods. However, the C-t measurements, the results of which are presented in figure (24), show that one difference exists which is indicated by the presence of the "lump" in the profile of the A structure. It is possible that a relation exists between the presence of this anomaly in the Zerbst profile and the physical parameters of the interface states. As far as we know, this kind of profile has not been indentif ied previously and for the present we are holding back on any new interpretation.

VI.3. Effect of electrical stresses on the MNOS structures

In the structures of the MNOS type (metal-nitride-oxide-semiconductor), because of the importance of the thickness of the oxide (nitride + SiO2 ~ 1000 A), large voltages were necessary so that the effects of the electrical stress on the profile could be observed. The experimental approach adopted consists of applying a constant voltage over a set period of time. The results obtained from the study of these structures are shown in figure (25). In the first instance it is found, as previously, that the effects of the stress in accumulation(a negative voltage applied t& the substrate of type n) are slight. With regard to the effect of stress in depletion (a positive voltage applied to the substrate of type n), the effect is greater and non-cumulative, i.e. the increase of saturates with the injected charge (Fig. 26). Above a certain stress (2 to 3 MV/cm - l00s), the normal curve for this type of structure, where ~ quasi-independent of N₁, changes after the stress into a profile corresponding to a decreasing function..

Ct5.jpg illustrate the kind of measurments.

References: 1) M. zerbst, Z. Angew. Phys. 12 30 (1966).2) D.W. Small and R.F. Pierret, Sol. State Electr. 19 505 (1976).

3)F.P. Heiman, IEEE Trans. Electron Device ED-14, 781 (1967).

4)D.R. Wolters and J.J. van der Schoot, J. Appi. Phys. 58 831 (1985).

5)T.W. Collins and J.N. Churchill, IEEE ED-22, 90 (1975).

6) A. Yankova, L. DoThanh and P. Balk, Sol. State Electronics 30, 939 (1987).