Report on the effects of Rf-sputtering of Fe on Gate oxide layer of MOS structures encapsulated by Silicon Oxynitride.

During my stay at the university of Twente, department of electrical engineering sensor group, I had the opportunity to work with a colleague K.Aite. He performed for me some oxidations and one PECVD SiON deposition at the electronic laboratory ICE.

Please find hereafter a copy of a report on this cooperation. My opinion is that the available data from Aite on the oxidation conditions and SiON deposition are insufficient and incorrect. If you share my opinion, it will be the first step for further negotiations about writing an expert report. Your opinion may be needed in another questions which are obvious for every scientist, among them the fact that a low magnetic field ( 1-3 Oe) has no detectable effect on the electrical parameters (at room temperature) of a MOS structure, and that the integration of a NiFe thin film angle detector with CMOS electronic amplifier on a single chip (smart sensor) is not a realistic and one researcher project.

Report on the effects of Rf-sputtering of Fe on Gate oxide layer of MOS structures encapsulated by Silicon Oxynitride.

In order to clarify this story i choose a suitable introduction to make this report logical to some extent. The reality is professor Wallinga (not my official superior) did everything he can to prevent my research activities. It was an order from hem to start my research with a design of a CMOS amplifier which was not relevant to my research and far from my education/specialty ( i graduated at Orsay faculty in physics-materials science with a degree from Jussieu in semiconductor technology ). It tooks me 6 months of my 2 years stay at this university to do the damn job, simulation and layout. It was not enough for the guy to came after this with another stupid initiative like ordering a research on Fe contamination, which deserve some consideration but not at experimental research. This was the reason to investgate Fe sputtering instead of NiFe the material of the angle detector sensor. Further you will notice the use of some archaic analysis method for electrical characterisation. Better techniques were available but not accessible, it was their way to prevent me to publish any results about my research. You will find an abstract about my first year stay, the second year was as planned by Wallinga and Fluitman a "conflict" year. Aite a researcher of Wallinga group refused to write a report on his participation in my research, therefore i was unable to interpretate correctly the results of this preleminary research. Further Wallinga prevents my access to his Lab to continue the job. During the second year, they were busy with their patent applications and publications. He gave me the feeling that he was confident that what Aite published was the ultimate solution of the smart sensor research and a sign of better and wealthy future.

Introduction.

Conventional Rf-sputtering is a versatile technique for thin film deposition with controlled properties. An applied negative bias during Rf-sputtering, enhances the ion bombardment of the growing film, affecting the structure and hence its physical properties. Different authors have pointed out the advantages of Rf bias sputtering. However this technique has drawbacks and shortcomings, especially when deposition is performed on electrically sensitive devices such as MOSFET's and MOS capacitors. Exposure of SiO2-Si structures to a high voltage plasma causes extensive radiation damage and induces charging in the dielectric film. Furthermore, during ions bombardment and film condensation, excessive heating of the substrate may occur, accelerating stresses inducing instabilities in these structures. Uncapped MOS capacitors are not suitable for such investigations, since ion bombardment is known to enhance the mobile ions difflusion leading to erratic electrical measurements.

In this preliminary study, we report our results on Rf~bias sputtering Fe effects on the electrical properties of PECVD SiON passivated capacitors. For a particular composition, SiON have proved to have a very low amount of mobile charge under temperature-bias stress, and to be a highly resistant to ionizing radiation. The deposition parameters of PECVD SiON have been extensively investigated by C.M.Denisse, al, University of Utrecht (1986).(doc.1)

Sample preparation.

Classical Silicon oxidations and PECVD SiON deposition have been performed at ICE-Lab Twente by K.Aite. Three types of MOS diodes were prepared. Only the third one was encapsulated by SiON in order to investigate sputtering damage. The available data on oxidation and SiON deposition are given in the next pages. Oxidation parameters for run. 1 and run.3 are still missing, and the apparatus used in the PECVD step is unknown. The MOS structures (MOS.jpg) were prepared by electron evaporation of AL contacts defined by conventional photo-lithography. Following backside metalization, a 30 minutes annealing was performed in N2 at 450C.

These experiments weere carried out at the sensor laboratory of TDM group. The electrical characterization was performed using high frequency CV, quasistatic CV, and capacitance-transient C-t methods.

SiON depositions were performed after electrical charcterization. A commercial Leybold-Heraeus Rf- sputtering unit (type Z400 ) was used for Fe sputtering. The target had a diameter of 10 cm, the target-substrate distance was 5 cm, the target voltage 1 KV, and the substrate bias 80 V.

After sputtering, and annealing (400 C-30 minutes in N2) the electrical measurements were performed. The investigated MOS structures were characterized again twice within the next fifth month.

Available data : Aite1.jpg and AITE3.jpg are the only available data on the oxidation and PECVD deposition received from Aite. The second document was sent to Prof.Fluitman 2 months before i left the university.

Results :

CV3.htm : resume of CV data of this experiment.

Run1.

-Structure : MOS capacitors, oxide color blue.

-4 wafers : A0, A1, A2, and A3.

-Date : December 88 - January 89.

-Result : run1.jpg shows the CV and C-t recordings after relaxation (~3 months).

-Remarks : The oxidation conditions of this run are still missing. Most of the structures of wafer 0 were defective, possibly from being subjected to a heavy implantation step. As suggested by Aite, this wafer was also encapsulated by SiON as in run.3.

Run.2

-Structure : MOS capacitors, oxide color silicon.

- Date : February 89.

-2 wafers : Cs-Cns.

-Remarks : Oxidation conditions given on 06-02-89, structures of Cns were defective, oxide was too thin!!!

Run.3

-Structure : MOS capacitors covered with SiON with different chemical compositions (MOS.jpg) , oxide color red.

-Date : May-June 89.

-7 wafers : A0/B0 (run 1), B1,B2,B3,B4,B5,B6.

-Results : The C-t relaxation times of this run are ploted in C-t 3.jpg On the page Auger.jpg are included Auger profilings of wafers 2 and 5.

-Remarks : Oxidation conditions are still missing. PECVD apparatus unknown. Before the investigation of the electrical measurements, Aite expected passivation in wafers 3, 5, and 6. This was the reason why we performed subsequent CV-Ct measurements later, consisting in room temperature annealing. The anneal step at 400C could not remove the fast surface states of wafer 4. C-t measurements were not possible.

Interpretation :

CV3.htm shows that the oxidation conditions of the 3 runs were different, thickness of run 1 was 1100A (A0 was only 840), run 2 200A/70A , and run 3 700A (A=angstrom). Concerning the wafer A0, how is it possible to grow a blue SiO2 layer 840A thick? the color of SiO2 at various ranges of film thickness is available in Sze "physics of semiconductor devices" book Doc2. The color of A0 should be red. This suggest a heavy nitridation of the oxide of wafer 0. Since Mister Aite in his ridiculous patent application propose the world a new passivation technique using N2/NH3 50Khz plasma, which in the same time passivate and create a SiN layer on top of your device, you understand why "my blue A0 wafer" only 840 A thick is. The Zerbst profile of the C-t measurment show a strange "humb", which i once detected in implanted MOS devices i investigated at Philips NatLab Ct5.jpg

Further, in this preliminary investigation, we would expect lifetime to decrease after sputtering or Fe contamination. However, we discovered that the time constant for a deep depleted MOS capacitor to recover to its inverted state (referred to as C-t relaxation time) is increased dramatically in wafers of run. 1, and in wafers 3, 5, and 6 of run 3. The corresponding C-t curves are unusual. The Ct electrical parameters were found nearly constant in wafers 0, 1, and 2 of run.3. Hydrogen could account for the reduction of some defects. The observed decrease in Cmin/Cmax could be explained with the model of carrier compensation phenomenon (See.Panwar et al). However its introduction is not clear. It could be liberated from the SiON layer, but wafers of run. 1, were not encapsulated by SiON.

Furthermore, SiON of wafers 1, 2, and 3 of run.3 is classified as an 0-type where hydrogen is stable, thus the results of wafer. 3 are conflicting. See doc.3 treating similar investigation with Cl and X-ray.

Another explanation for the dramatical increase of the Ct relaxation time could be the introduction of Fluorine during wafers cleaning, as it has been suggested from the oxidation conditions of run.2 ( AITE3.jpg ) . But, the oxidation conditions of both run. 1 and run.3 are still missing. Should that be the case, then how to explain my results which show the absence of passivation phenomenon in wafers 0, 1 and 2 of run. 3. Further, It is known, that relaxations due to Fluorine take place in a couple of hours or days (doc.3), but the relaxations observed in this study took place at room-temperature in a period of several months (6 months).

The Auger profilings ( If not manipulated by Dr.Hannekamp group) confirm the presence of Nitrogen in the gate oxide of wafer 6 Auger.jpg. The origin of the detected Nitrogen is unclear. It is well known that nitridation in N2 ambient of Si02 is difficult and requires a high temperature above 1000C (doc 4 and 5), or should took place in a N2/NH3-plasma (doc.6). In run2 as this document suggests, the wafers were treated at lower temperature, higher pressures, or higher power densities because the SiO2 was etched off to a thickness of 200A/70A (as indicated by CV measurements and oxide color (silicon)). Another interesting result was the abscence of the well known fluctuations in the C-t measurements due to mobile ions difflusion ( Na), surface potential fluctuations etc. which means that the observed passivation was the result of an additional low temperature NH3 treatment process-step, and could not be associated with the well-known technological fluctuations (See Aite european patent application, europat.htm). It means also that plasma deposition took place in a clean machine, which Aite refuses to give any information about AITE3.jpg. In fact, he was working on an improved apparatus for PECVD processing with a reduced in the contamination amount (Aite et al, Us-patent 1991), Uspatent.jpg

The available data from Aite were insufficient and erroneous Aite1.jpg and AITE3.jpg, the available publication (Aite et al, 1990, doc.7.), Nl patent application (1989), european patent application (europat.htm, 1990) and US-patent (1991,doc) , Uspatent.jpg suggest that Aite used my wafers for his own and his colleagues research. These publications deal with a new plasma hydrogenation-nitridation of MOS structures at low temperature. The US patent concerns the design of a PECVD appparatus.

The only possible alternative interpretation is a sabotage act of my research. In this case passivation is aresult of SiON N-type nature as mentionned by Denisse et al. Only in this type of SiON the chemical reaction : Si-H + N-H ----------> Si-N + H2 took place. And what about nitrogen from wafer 6 ? In this case probably Dr.Hannekamp group manipulated the auger analysis by changing the measurements parameters during auger analysis, activating deliberatly nitrogen diffusion towards the Si-SiO2 interface as mentionned in Aite's publication. Or the "Aite" technique was really efficient and he used it in wafer 3 to camouflage the way to this suggestion and make my interpretation impossible. BTW, the experimental parameters of SiON deposition were inspired from Denisse work, only the deposition temperature and frequency were different (300C-50Khz instead of 400C-400Khz) which explain the activation of the above mentionned chemical reaction under heavy electrons bombardment during Fe sputtering.

I don't believe in miracles, but if it happen that i was wrong, university Twente put "itself" in accusation bank for these reasons :-They gave me an erroneous research task (integration of an angle detector) due to incompetence of their workers, - they prevent me to access the working area, -they performed some steps of my research and they refused to inform me about it, -they refuse to investigate my allegations, they prevent me to continue my research, they intimidate me and family members, they are guilty of slander and diffamations about my person. They can go to hell.

ELMRABAT.jpg is a copy my abstract for a congres resuming my first year research activity at the universityof Twente.

Acknowledgments

Doc.1: C.M.M. Denisse et al, J.Appl.Phys. 60, 1 October 1986.

Doc.2: Physics of semiconductor Devices, S.M.Sze, p.393.

Doc.3: Wang el al, Appl.Phys.Lett.,Vol.53, No 7, 15 Augustus 1988.

Doc.4: I.Mendez et al, J.Vac.Sci.Technol.B 6(1), Jan/Feb 1988.

Doc.5: A.E.T. Kuiper et al, Interface compositions of thin silicon nitride and oxynitride films as prepared by different growth techniques, in Insulating films on semiconductors(J.F.Verweij and D.R.Wlters(editors).

Doc.6: P.C.Fazan et al, J.Vac.Sci.Technol B6(4), Jul/Aug 1988

Doc.7: K.Aite, F.W.Ragay, J.Middelhoek, Electronics letters, 26, 1990. S.Panwar et al, Appl.Phys.Letter, 56, 2 April 1990. US patent 5,225, 375 May 20 1991.

The following publication are dealing with the same finding :

-European patent application nr. EP0405689A1. K.Aite, 1990 (Univerrsity of Twente)

-Duch application : K.Aite, F.W.Ragay, J.M.Middelhoek, R.Koekoek, 28/06/89.

-K.Aite, F.W.Ragay, J.Middelhoek, Electronics letters, 26, 1990.

Dr.B.Elmrabat. maroc@tomaatnet.nl

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